1. Field of the Invention
The disclosure generally relates to a clock and data recovery (CDR) circuit, and more particularly, relates to a CDR circuit for reducing bit error rate (BER).
2. Description of the Related Art
In the field of communication by optical fibers, a clock and data recovery (CDR) circuit is required for a receiver to recover received signals. Generally speaking, the CDR circuit comprises a phase locked loop (PLL) circuit which provides a control voltage for an oscillator. The CDR circuit is mainly configured to generate a recovery data and a recovery clock according to the received signals.
Traditionally, on account of variations in manufacturing processes, a CDR circuit often generates phase errors between the recovery data and the recovery clock, which increases bit error rate (BER). For solving the foregoing problem, it is required that a new CDR circuit is designed so as to improve phase alignment and reduce BER.